View LTC14001_4292880.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Complete 12-Bit ADC in SO-8 Single Supply 5V or 5V Operation Sample Rate: 400ksps Power Dissipation: 75mW (Typ) 72dB S/(N + D) and -80dB THD at Nyquist No Missing Codes over Temperature Nap Mode with Instant Wake-Up: 6mW Sleep Mode: 30W High Impedance Analog Input Input Range (1mV/LSB): 0V to 4.096V or 2.048V Internal Reference Can Be Overdriven Externally 3-Wire Interface to DSPs and Processors (SPI and MICROWIRETM Compatible)
The LTC(R)1400 is a complete 400ksps, 12-bit A/D converter which draws only 75mW from 5V or 5V supplies. This easy-to-use device comes complete with a 200ns sampleand-hold and a precision reference. Unipolar and bipolar conversion modes add to the flexibility of the ADC. The LTC1400 has two power saving modes: Nap and Sleep. In Nap mode, it consumes only 6mW of power and can wake up and convert immediately. In the Sleep mode, it consumes 30W of power typically. Upon power-up from Sleep mode, a reference ready (REFRDY) signal is available in the serial data word to indicate that the reference has settled and the chip is ready to convert. The LTC1400 converts 0V to 4.096V unipolar inputs from a single 5V supply and 2.048V bipolar inputs from 5V supplies. Maximum DC specs include 1LSB INL, 1LSB DNL and 45ppm/C drift over temperature. Guaranteed AC performance includes 70dB S/(N + D) and -76dB THD at an input frequency of 100kHz, over temperature. The 3-wire serial port allows compact and efficient data transfer to a wide range of microprocessors, microcontrollers and DSPs.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
APPLICATIO S

High Speed Data Acquisition Digital Signal Processing Multiplexed Data Acquisition Systems Audio and Telecom Processing Digital Radio Spectrum Analysis Low Power and Battery-Operated Systems Handheld or Portable Instruments
Single 5V Supply, 400kHz, 12-Bit Sampling A/D Converter
5V SUPPLY CURRENT (mA)
+
ANALOG INPUT (0V TO 4.096V) 2.42V REFOUT 10F
VCC 10F 0.1F LTC1400 AIN VREF 0.1F GND
+
U
TYPICAL APPLICATIO
Power Consumption vs Sample Rate
100 NORMAL CONVERSION NAP MODE BETWEEN CONVERSION SLEEP AND NAP MODE BETWEEN CONVERSION SLEEP MODE BETWEEN CONVERSION 6.4MHz CLOCK
10 VSS MPU P1.4 P1.3 SERIAL DATA LINK P1.2
1
CONV CLK DOUT
0.1
0.01
1400 TA01
0.001 0.01 0.1
U
FEATURES
LTC1400 Complete SO-8, 12-Bit, 400ksps ADC with Shutdown DESCRIPTIO
U
1
10 100 1k 10k 100k 1M SAMPLE RATE (Hz)
1400 TA02
1400fa
1
LTC1400
(Note 1, 2)
Supply Voltage (VCC) ..................................................7V Negative Supply Voltage (VSS) ..................... -6V to GND Total Supply Voltage (VCC to VSS) Bipolar Operation Only ..........................................12V Analog Input Voltage (Note 3) Unipolar Operation ....................-0.3V to (VCC + 0.3V) Bipolar Operation ........... (VSS - 0.3V) to (VCC + 0.3V) Digital Input Voltage (Note 4) Unipolar Operation ................................. -0.3V to 12V Bipolar Operation .........................(VSS - 0.3V) to 12V Digital Output Voltage Unipolar Operation ....................-0.3V to (VCC + 0.3V) Bipolar Operation ........... (VSS - 0.3V) to (VCC + 0.3V) Power Dissipation .............................................. 500mW Operation Temperature Range LTC1400C ................................................ 0C to 70C LTC1400I ............................................. -40C to 85C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
TOP VIEW VCC 1 AIN 2 VREF 3 GND 4 8 VSS 7 CONV 6 CLK 5 DOUT
S8 PACKAGE 8-LEAD PLASTIC SO TJMAX = 150C, JA = 130C/W
ORDER PART NUMBER LTC1400CS8 LTC1400IS8
S8 PART MARKING 1400 1400I
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
POWER REQUIRE E TS
SYMBOL VCC VSS ICC ISS PD PARAMETER
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C unless otherwise noted. (Note 5)
CONDITIONS Unipolar Bipolar Bipolar Only fSAMPLE = 400ksps Nap Mode Sleep Mode fSAMPLE = 400ksps, VSS = -5V Nap Mode Sleep Mode fSAMPLE = 400ksps Nap Mode Sleep Mode

MIN 4.75 4.75 -2.45
TYP
MAX 5.25 5.25 -5.25
UNITS V V V mA mA A mA mA A mW mW W
Positive Supply Voltage (Note 6) Negative Supply Voltage (Note 6) Positive Supply Current
15 1.0 5.0 0.3 0.2 1 75 6 30
30 3.0 20.0 0.6 0.5 5 160 20 125
Negative Supply Current
Power Dissipation
A ALOG I PUT
SYMBOL VIN IIN CIN PARAMETER
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C unless otherwise noted. (Note 5)
CONDITIONS 4.75V VCC 5.25V (Unipolar) 4.75V VCC 5.25V, -5.25V VSS -2.45V (Bipolar) During Conversions (Hold Mode) Between Conversions (Sample Mode) During Conversions (Hold Mode)

MIN
TYP 0 to 4.096 2.048
MAX
UNITS V V
Analog Input Range (Note 7) Analog Input Leakage Current Analog Input Capacitance
1 45 5
1400fa
2
U
A pF pF
W
U
U
WW UW
W
ABSOLUTE
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
U
U
LTC1400 CO VERTER CHARACTERISTICS
PARAMETER Resolution (No Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Full-Scale Error Full-Scale Tempco IOUT(REF) = 0
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C unless otherwise noted. With internal reference (Notes 5, 8)
CONDITIONS
DY A IC ACCURACY
SYMBOL S/(N + D)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 5V, VSS = -5V, fSAMPLE = 400kHz unless otherwise noted. (Note 5)
PARAMETER Signal-to-Noise Plus Distortion Ratio Total Harmonic Distortion Up to 5th Harmonic Peak Harmonic or Spurious Noise CONDITIONS 100kHz Input Signal 200kHz Input Signal Commercial Industrial

THD
IMD
I TER AL REFERE CE CHARACTERISTICS
PARAMETER VREF Output Voltage VREF Output Tempco VREF Load Regulation VREF Load Regulation VREF Wake-Up Time from Sleep Mode (Note 7)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C unless otherwise noted. (Note 5)
CONDITIONS IOUT = 0 IOUT = 0 4.75V VCC 5.25V -5.25V VSS 0V 0 |IOUT| 1mA CVREF = 10F
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VIH VIL IIN CIN VOH PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C unless otherwise noted. (Note 5)
CONDITIONS VCC = 5.25V VCC = 4.75V VIN = 0V to VCC VCC = 4.75V, IO = -10A VCC = 4.75V, IO = -200A

U
U
U
WU
U
U
MIN 12

TYP
MAX 1 1 6 8 15
UNITS Bits LSB LSB LSB LSB LSB ppm/C
(Note 9) (Note 10)
10
45
MIN 70 69
TYP 72 72
MAX
UNITS dB dB dB
100kHz Input Signal 200kHz Input Signal 100kHz Input Signal 200kHz Input Signal fIN1 = 99.51kHz, fIN2 = 102.44kHz fIN1 = 199.12kHz, fIN2 = 202.05kHz

-82 -80 -84 -82 -82 -70 4 900
-76 -76
dB dB dB dB dB dB MHz kHz
Intermodulation Distortion Full Power Bandwidth Full Linear Bandwidth (S/(N + D) 68dB)
U
MIN 2.400
TYP 2.420 10 0.01 0.01 2 4
MAX 2.440 45
UNITS V ppm/C LSB/V LSB/V LSB/mA ms
MIN 2.0
TYP
MAX 0.8 10
UNITS V V A pF V V
1400fa
5
4.0
4.7
3
LTC1400 DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL VOL IOZ COZ ISOURCE ISINK PARAMETER Low Level Output Voltage Hi-Z Output Leakage DOUT Hi-Z Output Capacitance DOUT (Note 7) Output Source Current Output Sink Current VOUT = 0V VOUT = VCC
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C unless otherwise noted. (Note 5)
CONDITIONS VCC = 4.75V, IO = 160A VCC = 4.75V, IO = 1.6mA VOUT = 0V to VCC

TI I G CHARACTERISTICS
SYMBOL tCONV tACQ fCLK tCLK tWK(NAP) t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 fSAMPLE(MAX) Maximum Sampling Frequency Conversion Time Acquisition Time CLK Frequency CLK Pulse Width Time to Wake Up from Nap Mode
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C unless otherwise noted. (Note 5)
PARAMETER CONDITIONS (Note 6) fCLK = 6.4MHz (Unipolar Mode) (Bipolar Mode VSS = -5V) (Note 7)

CLK Pulse Width to Return to Active Mode CONV to CLK Setup Time CONV After Leading CLK CONV Pulse Width Time from CLK to Sample Mode Aperture Delay of Sample-and-Hold Minimum Delay Between Conversion Delay Time, CLK to DOUT Valid Delay Time, CLK to DOUT Hi-Z Time from Previous Data Remains Valid After CLK Minimum Time between Nap/Sleep Request to Wake Up Request (Unipolar Mode) (Bipolar Mode VSS = -5V) CLOAD = 20pF CLOAD = 20pF CLOAD = 20pF (Notes 7, 12) (Note 11) (Note 7) Jitter < 50ps (Note 7)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to GND. Note 3: When these pin voltages are taken below VSS (ground for unipolar mode) or above VCC, they will be clamped by internal diodes. This product can handle input currents greater than 40mA below VSS (ground for unipolar mode) or above VCC without latch-up. Note 4: When these pin voltages are taken below VSS (ground for unipolar mode), they will be clamped by internal diodes. This product can handle input currents greater than 40mA below VSS (ground for unipolar mode) without latch-up. These pins are not clamped to VCC. Note 5: VCC = 5V, fSAMPLE = 400kHz, tr = tf = 5ns unless otherwise specified. Note 6: Recommended operating conditions.
4
U
U
MIN
TYP 0.05 0.10 15 -10 10
MAX 0.4 10
UNITS V V A pF mA mA
UW
MIN 400
TYP
MAX 2.1
UNITS kHz s ns ns MHz ns ns ns ns ns ns
230 200 0.1 50 350 50 80 0 50 80 45 265 235 40 40 14 50 25
300 270 6.4
(Notes 7, 12) (Note 7)

ns 65 385 355 80 80 ns ns ns ns ns ns ns

Note 7: Guaranteed by design, not subject to test. Note 8: Linearity, offset and full-scale specifications apply for unipolar and bipolar modes. Note 9: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 10: Bipolar offset is the offset voltage measured from -0.5LSB when the output code flickers between 0000 0000 0000 and 1111 1111 1111. Note 11: The rising edge of CONV starts a conversion. If CONV returns low at a bit decision point during the conversion, it can create small errors. For best performance ensure that CONV returns low either within 120ns after conversion starts (i.e., before the first bit decision) or after the 14 clock cycle. (Figure 13 Timing Diagram). Note 12: If this timing specification is not met, the device may not respond to a request for a conversion. To recover from this condition a NAP request is required.
1400fa
LTC1400 TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity vs Output Code
1.00 DIFFERENTIAL NONLINEARITY (LSBs) 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
1400 TPC01
fSAMPLE = 400kHz INTEGRAL NONLINEARITY (LSBs)
SIGNAL/(NOISE + DISTORTION) (dB)
Signal-to-Noise Ratio (Without Harmonics) vs Input Frequency
80 SPURIOUS-FREE DYNAMIC RANGE (dB) 70 SIGNAL-TO-NOISE RATIO (dB) 60 50 40 30 20 10 0 10 fSAMPLE = 400kHz 100 INPUT FREQUENCY (kHz) 1000
1400 TPC07
-30 -40 -50 -60 -70 -80 -90 10 100 INPUT FREQUENCY (kHz) 1000
1400 TPC08
ACQUISITION TIME (ns)
AMPLITUDE OF POWER SUPPLY FEEDTHROUGH (dB)
Reference Voltage vs Load Current
2.435 2,430 REFERENCE VOLTAGE (V) 2.425 2.420 2.415 2.410 2.405 2.400 2.395 2.390 -8 -7 -6 -5 -4 -3 -2 -1 LOAD CURRENT (mA) 0 1 2
-30 -40 -50 -60 -70 -80 -90 1 VCC (VRIPPLE = 1mV) 10 100 RIPPLE FREQUENCY (kHz) 1000
1400 TPC07.5
SUPPLY CURRENT (mA)
UW
1400 TPC03
Integral Nonlinearity vs Output Code
1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0 512 1024 1536 2048 2560 3072 3584 4096 OUTPUT CODE
1400 TPC02
S/(N + D) vs Input Frequency and Amplitude
80 70 60 50 40 30 20 10 0 10 VIN = - 60dB fSAMPLE = 400kHz 100 INPUT FREQUENCY (kHz) 1000
1400 TPC06
fSAMPLE = 400kHz
VIN = 0dB
VIN = -20dB
Peak Harmonic or Spurious Noise vs Input Frequency
0 -10 -20 fSAMPLE = 400kHz 4500 4000 3500 3000 2500 2000 1500 1000 500 0
Acquisition Time vs Source Impedance
TA = 25C
-100
10
100 1000 RSOURCE ()
10000
1400 TPC05
Power Supply Feedthrough vs Ripple Frequency
0 -10 -20 fSAMPLE = 400kHz 20
Supply Current vs Temperature
fSAMPLE = 400kHz
15
10
VSS (VRIPPLE = 10mV)
5
-100
0 -50 -25
0 25 50 75 TEMPERATURE (C)
100
125
1400 TPC04
1400fa
5
LTC1400 PI FU CTIO S
VCC (Pin 1): Positive Supply, 5V. Bypass to GND (10F tantalum in parallel with 0.1F ceramic). AIN (Pin 2): Analog Input. 0V to 4.096V (Unipolar), 2.048V (Bipolar). VREF (Pin 3): 2.42V Reference Output. Bypass to GND (10F tantalum in parallel with 0.1F ceramic). GND (Pin 4): Ground. GND should be tied directly to an analog ground plane. DOUT (Pin 5): The A/D conversion result is shifted out from this pin.
AIN
VREF 2.42V REF
CLK CONV CONTROL LOGIC
SUCCESSIVE APPROXIMATION REGISTER/PARALLEL TO SERIAL CONVERTER
TEST CIRCUITS
5V 3k DOUT 3k CLOAD DOUT CLOAD
Hi-Z TO VOH VOL TO VOH VOH TO Hi-Z
6
W
FU CTIO AL BLOCK DIAGRA U U
U
U
U
CLK (Pin 6): Clock. This clock synchronizes the serial data transfer. A minimum CLK pulse of 50ns will cause the ADC to wake up from Nap or Sleep mode. CONV (Pin 7): Conversion Start Signal. This active high signal starts a conversion on its rising edge. Keeping CLK low and pulsing CONV two/four times will put the ADC into Nap/Sleep mode. VSS (Pin 8): Negative Supply. -5V for bipolar operation. Bypass to GND with 0.1F ceramic. VSS should be tied to GND for unipolar operation.
CSAMPLE
ZEROING SWITCH VCC GND VSS
12-BIT CAPACITIVE DAC
COMP
12
DOUT
1400 BD01
Hi-Z TO VOL VOH TO VOL VOL TO Hi-Z
1400 TC01
1400fa
LTC1400
Conversion Details The LTC1400 uses a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-bit serial output based on a precision internal reference. The control logic provides easy interface to microprocessors and DSPs through 3-wire connections. A rising edge on the CONV input starts a conversion. At the start of a conversion the successive approximation register (SAR) is reset. Once a conversion cycle has begun it cannot be restarted. During conversion, the internal 12-bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). Referring to Figure 1, the AIN input connects to the sample-and-hold capacitor during the acquired phase and the comparator offset is nulled by the feedback switch. In this acquire phase, it typically takes 200ns for the sample-and-hold capacitor to acquire the analog signal. During the convert phase, the comparator feedback switch opens, putting the comparator into the compare mode. The input switches connect CSAMPLE to ground, injecting the analog input charge onto the summing junction. This input charge is successively compared with the binary-weighted charges supplied by the capacitive DAC. Bit decisions are made by the high speed comparator. At the end of a conversion, the DAC output balances the AIN input charge. The SAR contents (a 12-bit data word) which represent the input voltage, are output through the serial pin DOUT.
SAMPLE S1
AMPLITUDE (dB)
CDAC VDAC
Figure 1. AIN Input
1400fa
+
HOLD
DAC
-
AIN
SAMPLE
CSAMPLE
COMP
U
Dynamic Performance The LTC1400 has excellent high speed sampling capability. FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figure 2a shows a typical LTC1400 FFT plot. Signal-to-Noise Ratio The signal-to-noise plus distortion ratio [S/(N + D)] is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from DC to half the sampling frequency. Figure 2a shows a typical spectral content with a 400kHz sampling rate and a 100kHz input. The dynamic performance is excellent for input frequencies up to the Nyquist limit of 200kHz as shown in Figure 2b.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz)
1400 F02a
APPLICATIO S I FOR ATIO W UU
fSAMPLE = 400kHz fIN = 94.824kHz SINAD = 72.5dB THD = - 82dB
Figure 2a. LTC1400 Nonaveraged, 4096 Point FFT Plot with 100kHz Input Frequency in Bipolar Mode
Effective Number of Bits
S A R DOUT
1400 F01
The effective number of bits (ENOBs) is a measurement of the effective resolution of an ADC and is directly related to the S/(N + D) by the equation: N= S / (N + D) - 1.76 6.02
7
LTC1400
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 - 60 -70 -80 -90 -100 -110 -120 AMPLITUDE (dB BELOW THE FUNDAMENTAL) 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz)
1400 F02b
fSAMPLE = 400kHz fIN = 199.121kHz SINAD = 72.1dB THD = - 80dB
Figure 2b. LTC1400 Nonaveraged, 4096 Point FFT Plot with 200kHz Input Frequency in Bipolar Mode
where N is the effective number of bits of resolution and S/(N + D) is expressed in dB. At the maximum sampling rate of 400kHz, the LTC1400 maintains very good ENOBs up to the Nyquist input frequency of 200kHz (refer to Figure 3).
12 11 EFFECTIVE NUMBER OF BITS 10 9 8 7 6 5 4 3 2 1 fSAMPLE = 400kHz 0 10k 100k INPUT FREQUENCY (Hz) NYQUIST FREQUENCY 74 68 62 56 50 SIGNAL/(NOISE + DISTORTION) (dB)
1M
1400 F03
Figure 3. Effective Bits and Signal-to-Noise + Distortion vs Input Frequency in Bipolar Mode
Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half of the sampling frequency. THD is expressed as:
8
U
THD = 20 log V22 + V32 + V 42 +... Vn2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through Vn are the amplitudes of the second through nth harmonics. THD vs input frequency is shown in Figure 4. The LTC1400 has good distortion performance up to the Nyquist frequency and beyond.
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 10k 3RD HARMONIC THD fSAMPLE = 400kHz 2ND HARMONIC 100k INPUT FREQUENCY (Hz) 1M
1400 F04
APPLICATIO S I FOR ATIO W U U
Figure 4. Distortion vs Input Frequency in Bipolar Mode
Intermodulation Distortion If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at sum and difference frequencies of mfa nfb, where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa + fb) and (fa - fb) while the 3rd order IMD terms includes (2fa + fb), (2fa - fb), (fa + 2fb) and (fa - 2fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula. IMD( fa fb) = 20log Amplitude at (fa fb) Amplitude at fa
1400fa
LTC1400
0 -10 -20 -30 AMPLITUDE (dB) -40 -50 - 60 -70 -80 -90 -100 -110 -120 0 20 40 60 80 100 120 140 160 180 200 FREQUENCY (kHz)
1400 F05
fSAMPLE = 400kHz fa = 99.512kHz fb = 102.441kHz fa fb 3fa 2fa 2fb - fa fa + fb 2fb
2fa + fb 2fa - fb 2fb + fa fb - fa 3fb
Figure 5. Intermodulation Distortion Plot in Bipolar Mode
Figure 5 shows the IMD performance at a 100kHz input. Peak Harmonic or Spurious Noise The peak harmonic or spurious noise is the largest spectral component excluding the input signal and DC. This value is expressed in decibels relative to the RMS value of a full-scale input signal. Full Power and Full Linear Bandwidth The full power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full linear bandwidth is the input frequency at which the S/(N + D) has dropped to 68dB (11 effective bits). The LTC1400 has been designed to optimize input bandwidth, allowing the ADC to undersample input signals with frequencies above the converter's Nyquist Frequency. The noise floor stays very low at high frequencies; S/(N + D) becomes dominated by distortion at frequencies far beyond Nyquist. Driving the Analog Input The analog input of the LTC1400 is easy to drive. It draws only one small current spike while charging the sampleand-hold capacitor at the end of a conversion. During conversion, the analog input draws only a small leakage current. The only requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. Any op amp that
U
settles in 200ns to small load current transient will allow maximum speed operation. If a slower op amp is used, more settling time can be provided by increasing the time between conversions. Suitable devices capable of driving the ADC's AIN input include the LT(R)1360 and the LT1363 op amps. LTC1400 comes with a built-in unipolar/bipolar detection circuit. If VSS potential is forced below GND, the internal circuitry will automatically switch to bipolar mode. The following list is a summary of the op amps that are suitable for driving the LTC1400, more detailed information is available in the Linear Technology databooks or the Linear Technology Website. LT1215/LT1216: Dual and quad 23MHz, 50V/s single supply op amps. Single 5V to 15V supplies, 6.6mA specifications, 90ns settling to 0.5LSB. LT1223: 100MHz video current feedback amplifier. 5V to 15V supplies, 6mA supply current. Low distortion up to and above 400kHz. Low noise. Good for AC applications. LT1227: 140MHz video current feedback amplifier. 5V to 15V supplies, 10mA supply current. Lowest distortion at frequencies above 400kHz. Low noise. Best for AC applications. LT1229/LT1230: Dual and quad 100MHz current feedback amplifiers. 2V to 15V supplies, 6mA supply current each amplifier. Low noise. Good AC specs. LT1360: 37MHz voltage feedback amplifier. 5V to 15V supplies. 3.8mA supply current. Good AC and DC specs. 70ns settling to 0.5LSB. LT1363: 50MHz, 450V/s op amps. 5V to 15V supplies. 6.3mA supply current. Good AC and DC specs. 60ns settling to 0.5LSB. LT1364/LT1365: Dual and quad 50MHz, 450V/s op amps. 5V to 15V supplies, 6.3mA supply current per amplifier. 60ns settling to 0.5LSB. Internal Reference The LTC1400 has an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory
1400fa
APPLICATIO S I FOR ATIO W U U
9
LTC1400
trimmed to 2.42V. It is internally connected to the DAC and is available at Pin 3 to provide up to 1mA of current to an external load. For minimum code transition noise, the reference output should be decoupled with a capacitor to filter wideband noise from the reference (10F tantalum in parallel with a 0.1F ceramic). The VREF pin can be driven with a DAC or other means to provide input span adjustment in bipolar mode. The VREF pin must be driven to at least 2.45V to prevent conflict with the internal reference. The reference should not be driven to more than 5V. Figure 6 shows an LT1360 op amp driving the reference pin. Figure 7 shows a typical reference, the LT1019A-5 connected to the LTC1400. This will provide an improved drift (equal to the maximum 5ppm/C of the LT1019A5) and a 4.231V full scale. If VREF is forced lower than 2.42V, the REFRDY bit in the serial data output will be forced to low.
5V INPUT RANGE 0.846 * VREF(OUT) AIN VCC
OUTPUT CODE
+
LT1360
VREF(OUT) 2.45V 3 10F
VREF
-
GND VSS -5V
Figure 6. Driving the VREF with the LT1360 Op Amp
OUTPUT CODE
INPUT RANGE 4.231V (= 0.846 * VREF)
10V VIN
AIN
VOUT 3 10F
VREF
LT1019A-5
GND
GND VSS -5V
1400 F07
Figure 7. Supplying a 5V Reference Voltage to the LTC1400 with the LT1019A-5
10
U
Unipolar/Bipolar Operation and Adjustment Figure 8 shows the ideal input/output characteristics for the LTC1400. The code transitions occur midway between successive integer LSB values (i.e., 0.5LSB, 1.5LSB, 2.5LSB, ... FS - 1.5LSB). The output code is straight binary with 1LSB = 4.096V/4096 = 1mV. Figure 9 shows the input/output transfer characteristics for the bipolar mode in two's complement format.
111...111 111...110 111...101 111...100 1LSB = FS 4096 000...011 000...010 000...001 000...000 0V 1 LSB FS - 1LSB INPUT VOLTAGE (V)
1400 F08
APPLICATIO S I FOR ATIO W UU
UNIPOLAR ZERO
LTC1400
Figure 8. LTC1400 Unipolar Transfer Characteristics
011...111 011...110
1400 F06
BIPOLAR ZERO
000...001 000...000 111...111 111...110 100...001 100...000 -FS/2 -1 0V 1 LSB LSB INPUT VOLTAGE (V) FS/2 - 1LSB
11400 F09
5V VCC
LTC1400
Figure 9. LTC1400 Bipolar Transfer Characteristics
Unipolar Offset and Full-Scale Error Adjustments In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero. Figure 10a shows the extra components required for full-scale
1400fa
LTC1400 U
1400 F10a
APPLICATIO S I FOR ATIO
R1 50 VIN
+
A1 R2 10k
-
R4 100 LTC1400
R3 10k
FULL-SCALE ADJUST GND
ADDITIONAL PINS OMITTED FOR CLARITY 20LSB TRIM RANGE
Figure 10a. LTC1400 Full-Scale Adjust Circuit
ANALOG INPUT 0V TO 4.096V 5V R1 10k R2 10k
+
A1 AIN R4 100k R5 4.3k FULL-SCALE ADJUST R3 100k R7 100k
10k
-
R9 20
Figure 10b. LTC1400 Offset and Full-Scale Adjust Circuit
ANALOG INPUT 2.048V R1 10k R2 10k
+
A1 AIN R4 100k R5 4.3k FULL-SCALE ADJUST R3 100k R7 100k LTC1400
-
Figure 10c. LTC1400 Bipolar Offset and Full-Scale Adjust Circuit
W
UU
AIN
error adjustment. Figure 10b shows offset and full-scale adjustment. Offset error must be adjusted before fullscale error. Zero offset is achieved by applying 0.5mV (i.e., 0.5LSB) at the input and adjusting the offset trim until the LTC1400 output code flickers between 0000 0000 0000 and 0000 0000 0001. For zero full-scale error, apply an analog input of 4.0945V (FS - 1.5LSB or last code transition) at the input and adjust R5 until the LTC1400 output code flickers between 1111 1111 1110 and 1111 1111 1111. Bipolar Offset and Full-Scale Error Adjustments Bipolar offset and full-scale errors are adjusted in a similar fashion to the unipolar case. Bipolar offset error adjustment is achieved by applying an input voltage of -0.5mV (-0.5LSB) to the input in Figure 10c and adjusting the op amp until the ADC output code flickers between 0000 0000 0000 and 1111 1111 1111. For full-scale adjustment, an input voltage of 2.0465V (FS - 1.5LSBs) is applied to the input and R5 is adjusted until the output code flickers between 0111 1111 1110 and 0111 1111 1111. Board Layout and Bypassing To obtain the best performance from the LTC1400, a printed circuit board is required. Layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by GND. High quality tantalum and ceramic bypass capacitors should be used at the VCC and VREF pins as shown in the Typical Application on the first page of this data sheet. For the bipolar mode, a 0.1F ceramic provides adequate bypassing for the VSS pin. For optimum performance, a 10F surface mount AVX capacitor with a 0.1F ceramic is recommended for the VCC and VREF pins. The capacitors must be located as close to the pins as possible. The traces connecting the pins and the bypass capacitors must be kept short and should be made as wide as possible. In unipolar mode operation, VSS should be isolated from any noise source before shorting to the GND pin.
1400fa
LTC1400
5V
R6 400
R8 10k OFFSET ADJUST
1400 F10b
5V
R6 200
R8 20k OFFSET ADJUST
-5V
1400 F10c
11
LTC1400
Input signal leads to AIN and signal return leads from GND (Pin 4) should be kept as short as possible to minimize noise coupling. In applications where this is not possible, a shielded cable between source and ADC is recommended. Also, since any potential difference in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible.
ANALOG SUPPLY -5V GND 5V GND DIGITAL SUPPLY 5V
+
+
+
VSS
GND LTC1400
VCC
GND
DIGITAL CIRCUITRY
1400 F11
Figure 11. Power Supply Connection
Figure 11 shows the recommended system ground connections. All analog circuitry grounds should be terminated at
t11
CLK
t1
CONV
NAP
SLEEP
VREF
REFRDY
NOTE: NAP AND SLEEP ARE INTERNAL SIGNALS. REFRDY APPEARS AS A BIT IN THE DOUT WORD.
Figure 12. Nap Mode and Sleep Mode Waveforms
12
U
the LTC1400 GND pin. The ground return from the LTC1400 Pin 4 to the power supply should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feedthrough from the microprocessor to the successive approximation comparator. The problem can be eliminated by forcing the microprocessor into a Wait state during conversion or by using three-state buffers to isolate the ADC data bus. Power-Down Mode Upon power-up, the LTC1400 is initialized to the active state and is ready for conversion. However, the chip can be easily placed into the Nap or Sleep mode by exercising the right combination of CLK and CONV signal. In the Nap mode all power is off except the internal reference, which is still active and provides 2.42V output voltage to the other circuitry. In this mode, the ADC draws only 6mW of power instead of 75mW (for minimum power, the logic inputs must be within 500mV of the supply rails). The wake-up time from the Nap mode to the active mode is 350ns.
t11 VCC t1
1400 F12
APPLICATIO S I FOR ATIO W UU
1400fa
LTC1400
In the Sleep mode, power consumption is reduced to a minimum by cutting off the supply to all internal circuitry including the reference. Figure 12 shows the ways to power down the LTC1400. The chip can enter the Nap mode by keeping the CLK signal low and pulsing the CONV signal twice. For Sleep mode operation, CONV signal should be pulsed four times while CLK is kept low. The LTC1400 can be returned to active mode easily. The rising edge of CLK will wake-up the LTC1400. During the transition from Sleep mode to active mode, the VREF voltage ramp-up time is a function of the loading conditions. With a 10F bypass capacitor, the wake-up time from Sleep mode is typically 4ms. A REFRDY signal will be activated once the reference has settled and is ready for an A/D conversion. This REFRDY bit is output to the DOUT pin before the rest of the A/D converted code.
t2 t3 1 CLK t4 CONV t6 INTERNAL S/H STATUS SAMPLE HOLD tACQ SAMPLE t8 DOUT Hi-Z REFRDY D11 D10 D9 D8 D7 tCONV tSAMPLE
1400 F13
2
3
4
5
Figure 13. ADC Digital Timing Diagram
CLK t8 t 10
VIH
D OUT VOL
U
Digital Interface The digital interface requires only three digital lines. CLK and CONV are both inputs, and the DOUT output provides the conversion result in serial form. Figure 13 shows the digital timing diagram of the LTC1400 during the A/D conversion. The CONV rising edge starts the conversion. Once initiated, it can not be restarted until the conversion is completed. If the time from CONV signal to CLK rising edge is less than t2, the digital output will be delayed by one clock cycle. The digital output data is updated on the rising edge of the CLK line. DOUT data should be captured by the receiving system on the rising CLK edge. Data remains valid for a minimum time of t10 after the rising CLK edge to allow capture to occur.
t7 6 7 8 9 10 11 12 t5 13 14 15 1 2 HOLD D6 D5 D4 D3 D2 D1 D0 Hi-Z REFRDY CLK VIH t9 VOH D OUT 10%
1400 F14
APPLICATIO S I FOR ATIO W UU
90%
Figure 14. CLK to DOUT Delay
1400fa
13
LTC1400 TYPICAL APPLICATIO S
Hardware Interface to TMS320C50's TDM Serial Port (Frame Sync is Generated from TFSX)
TMS320C50 5V 1 0.1F UNIPOLAR INPUT 2 VCC AIN CLK 6 TCLKX TCLKR TFSX TFSR TDR
+
10F
Logic Analyzer Waveforms Show 3.2s Throughput Rate (Input Voltage = 3.046V, Output Code = 1011 1110 0110 = 304610)
Data from LTC1400 Loaded into TMS320C50's TRCV Register
X RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
1400 TA05c
Data Stored in TMS320C50's Memory (in Right Justified Format)
0 0 0 RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1400 TA05d
14
U
+
7 CONV LTC1400 5 3 VREF DOUT VSS 8 GND 4
10F
0.1F
1400 TA04a
1400fa
LTC1400 TYPICAL APPLICATIO S
THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO TMS320C50 FRAME SYNC PULSE IS GENERATED FROM TFSX *Initialization* .mmregs ;- - Initialized data memory to zero .ds 0F00h DATA0 .word 0 DATA1 .word 0 DATA2 .word 0 DATA3 .word 0 DATA4 .word 0 DATA5 .word 0 ;- - Set up the ISR vector .ps 080Ah rint : B RECEIVE xint : B TRANSMIT trnt : B TREC txnt : B TTRANX ;- - Setup the reset vector .ps 0A00h .entry START: ; Defines global symbolic names ; Initialize data to zero ; Begin sample data location ;. ; Location of data ;. ;. ; End sample data location ; Serial ports interrupts ; 0A; ; 0C; ; 0E; ; 10;
*TMS32C050 Initialization* SETC INTM ; Temporarily disable all interrupts LDP #0 ; Set data page pointer to zero OPL #0834h, PMST ; Set up the PMST status and control register LACC #0 SAMM CWSR ; Set software wait state to 0 SAMM PDWSR ; *Configure Serial Port* SPLK #0038h, TSPC ; Set TDM Serial Port ; TDM = 0 Stand Alone mode ; DLB = 0 Not loop back ; FO = 0 16 Bits ; FSM = 1 Burst Mode ; MCM = 1 CLKX is generated internally ; TXM = 1 FSX as output pin ; Put serial port into reset ; (XRST = RRST =0) SPLK #00F8h, TSPC ; Take Serial Port out of reset ; (XRST = RRST = 1) SPLK #0FFFFh, IFR ; Clear all the pending interrupts
U
TMS320C50 Code for Circuit
*Start Serial Communication* SACL TDXR ; Generate frame sync pulse SPLK #040h, IMR ; Turn on TRNT receiver interrupt CLRC INTM ; Enable interrupt CLRC SXM ; For Unipolar input, set for right shift ; with no sign extension MAR *AR7 ; Load the auxiliary register pointer with seven LAR AR7, #0F00h ; Load the auxiliary register seven with #0F00h ; as the begin address for data storage WAIT: NOP ; Wait for a receive interrupt NOP ; NOP ; SACL TDXR ; !! regenerate the frame sync pulse B WAIT ; ; - - - - - - - end of main program - - - - - - - - - - ; *Receiver Interrupt Service Routine* TREC: LAMM TRCV ; Load the data received from LTC1400 SFR ; Shift right two times SFR ; AND #1FFFh, 0 ; ANDed with #1FFFh ; For converting the data to right ; justified format ; SACL *+, 0 ; Write to data memory pointed by AR7 and ; increase the memory address by one LACC AR7 ; SUB #0F05h,0 ; Compare to end sample address #0F05h BCND END_TRCV, GEQ ; If the end sample address has exceeded jump to END_TRCV ; SPLK #040h, IMR ; Else Re-enable the TRNT receive interrupt RETE ; Return to main program and enable interrupt *After Obtained the Data from LTC1400, Program Jump to END_TRCV* END_TRCV: SPLK #002h, IMR ; Enable INT2 for program to halt CLRC INTM SUCCESS: B SUCCESS *Fill the Unused Interrupt with RETE, to avoid program get "lost"* TTRANX: RETE RECEIVE: RETE TRANSMIT: RETE INT2: B halt ; Halts the running CPU
1400fa
15
LTC1400 TYPICAL APPLICATIO S
LTC1400 Interface to ADSP2181's SPORT0 (Frame Sync is Generated from RFS0)
+
10F
Logic Analyzer Waveforms Show 2.88s Throughput Rate (Input Voltage = 2.240V, Output Code = 1000 1100 0000 = 224010)
X
RDY D11 D10
Data Stored in ADSP2181's Memory (Normal Mode, SLEN = D)
0 0 0 RDY D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
1400 TA05d
16
U
5V UNIPOLAR INPUT
1 2 0.1F
VCC AIN
CLK
6 7 5
ADSP2181 SCLKO RFSO DR0
+
CONV LTC1400 3 VREF DOUT VSS 8 GND 4
10F
0.1F
1400 TA05a
Data from LTC1400 (Normal Mode)
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
1400 TA05c
1400fa
LTC1400 TYPICAL APPLICATIO S
THIS PROGRAM DEMONSTRATES LTC1400 INTERFACE TO ADSP-2181 FRAME SYNC PULSE IS GENERATED FROM RFS0 /*Section 1: Initialization*/ .module/ram/abs = 0 adspltc; /*define the program module*/ jump start; /*jump over interrupt vectors*/ nop; nop; nop; rti; rti; rti; rti; /*code vectors here upon IRQ2 int*/ rti; rti; rti; rti; /*code vectors here upon IRQL1 int*/ rti; rti; rti; rti; /*code vectors here upon IRQL0 int*/ rti; rti; rti; rti; /*code vectors here upon SPORT0 TX int*/ ax0 = rx0; /*Section 5*/ dm (0x2000) = ax0; /*begin of SPORT0 receive interrupt*/ rti; /* */ /* */ /*end of SPORT0 receive interrupt*/ rti; rti; rti; rti; /*code vectors here upon /IRQE int*/ rti; rti; rti; rti; /*code vectors here upon BDMA interrupt*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 TX (IRQ1) int*/ rti; rti; rti; rti; /*code vectors here upon SPORT1 RX (IRQ0) int*/ rti; rti; rti; rti; /*code vectors here upon TIMER int*/ rti; rti; rti; rti; /*code vectors here upon POWER DOWN int*/ /*Section 2: Configure SPORT0*/ start: /*to configure SPORT0 control reg*/ /*SPORT0 address = 0X3FF6*/ /*RFS is used for frame sync generation*/ /*RFS0 is internal, TFS is not use*/ /*bit 0-3 = Slen*/ /*F = 15 = 1111*/ /*E = 14 = 1110*/ /*D = 13 = 1101*/ /*bit 4,5 data type right justified zero filled MSB*/ /*bit 6 INVRFS = 0*/ /*bit 7 INVTFS = 0*/ /*bit 8 IRFS = 1 receive internal frame sync*/ /*bit 9,10,11 are for TFS (don't care)*/ /*bit 12 TFSW = 1 receive is Normal mode*/ /*bit 13 RTFS = 1 receive is framed mode*/ /*bit 14 ISCLK internal = 1*/ /*bit 15 multichannel mode = 0*/ ax0 = 0x6B0D; /*normal mode, bit12 = 0*/ /*if alternate mode bit12 = 1, ax0 = 0x7F0E*/ dm (0x3FF6) =ax0;
U
ADSP2181 Code for Circuit
/*Section 3: configure CLKDIV and RFSDIV, setup interrupts*/ /*to configure CLKDIV reg*/ ax0 = 2; dm(0x3FF5) = ax0; /*set the serial clock divide modulus reg SCLKDIV*/ /*the input clock frequency = 16.67MHz*/ /*CLKOUT frequency = 2x = 33MHz*/ /*SCLK= 1/2*CLKOUT*1/(SCLKDIV+1)*/ /*for SCLKDIV = 2, SCLK = 33/6 = 5.5MHz*/ /*to Configure RFSDIV*/ ax0 = 15; /*set the RFSDIV reg = 15*/ /*= > the frame sync pulse for every 16 SCLK*/ /*if frame sync pulse in every 15 SCLK, ax0 = 14*/ dm(0x3FF4) = ax0; /*to setup interrupt*/ ifc = 0x0066; /*clear any extraneous SPORT interrupts*/ icntl = 0; /*IRQXB = level sensitivity*/ /*disable nesting interrupt*/ imask= 0x0020; /*bit 0 = timer int = 0*/ /*bit 1 = SPORT1 or IRQ0B int = 0*/ /*bit 2 = SPORT1 or IRQ1B int = 0*/ /*bit 3 = BDMA int = 0*/ /*bit 4 = IRQEB int = 0*/ /*bit 5 = SPORT0 receive int = 1*/ /*bit 6 = SPORT0 transmit int = 0*/ /*bit 7 = IRQ2B int = 0*/ /*enable SPORT0 receive interrupt*/ /*Section 4: Configure System Control Register and Start Communication*/ /*to configure system control reg*/ ax0 = dm(0x3FFF); /*read the system control reg*/ ay0 = 0xFFF0; ar = ax0 AND ay0; /*set wait state to zero*/ ay0 = 0x1000; ar = ar OR ay0; /*bit12 = 1, enable SPORT0*/ dm(0x3FFF) = ar; /*frame sync pulse regenerated automatically*/ cntr = 5000; do waitloop until ce; nop; nop; nop; nop; nop; nop; waitloop: nop; rts; .endmod;
1400fa
17
LTC1400 TYPICAL APPLICATIO S U
Quick Look Circuit for Converting Data to Parallel Format
5V 5V
+
1V CC 10F 0.1F 2
VSS 8 CONV 7 6 5 12 RCK 10 SRCLR
LTC1400 AIN CONV CLK DOUT
2.42V REFERENCE OUTPUT
ANALOG INPUT (0V TO 4.096V)
+
3V REF 4 GND
10F
0.1F
3-WIRE SERIAL INTERFACE LINK
QA QB 11 QC SRCK 74HC595 QD 14 QE SER QF 13 QG G QH QH' 10 SRCLR
15 1 2 3 4 5 6 7 9
D0 D1 D2 D3 D4 D5 D6 D7
12 CLK
QA QB 11 QC SRCK 74HC595 QD 14 SER QE QF 13 QG G QH QH'
RCK
15 1 2 3 4 5 6 7 9
D8 D9 D10 D11 REFRDY
1400 TA03
1400fa
18
0.010 - 0.020 x 45 (0.254 - 0.508)
0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.016 - 0.050 0.406 - 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
PACKAGE DESCRIPTIO
W
Dimensions in inches (millimeters) unless otherwise noted. S8 Package 8-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5 0.228 - 0.244 (5.791 - 6.197) 1 0.053 - 0.069 (1.346 - 1.752) 2 3 4 0.014 - 0.019 (0.355 - 0.483) 0.050 (1.270) BSC
BLOCK DIAGRA
LTC1400
0.150 - 0.157** (3.810 - 3.988)
0.004 - 0.010 (0.101 - 0.254)
SO8 0695
1400fa
19
LTC1400 TYPICAL APPLICATIO S U
LTC1400 Interface to TMS320C50
TMS320C50 5V 1 0.1F UNIPOLAR INPUT 2 VCC AIN CLK 6 TCLKX TCLKR TFSX TFSR TDR
+
10F
+
7 CONV LTC1400 5 3 VREF DOUT VSS 8 GND 4
10F
0.1F
1400 TA04a
LTC1400 Interface to ADSP2181
5V 1 0.1F UNIPOLAR INPUT 2 6 7 5 ADSP2181 SCLKO RFSO DR0
+
VCC AIN
CLK
10F
+
CONV LTC1400 3 VREF DOUT VSS 8 GND 4
10F
0.1F
1400 TA05a
RELATED PARTS
PART NUMBER LTC1285/LTC1288 LTC1286/LTC1298 LTC1290 LTC1296 LTC1403/LTC1403A LTC1407/LTC1407A LTC1417 LTC1609 LTC1860/LTC1861 LTC1864/LTC1864 DESCRIPTION 12-Bit, 3V, 7.5/6.6ksps, Micropower Serial ADCs 12-Bit, 5V 12.5/11.16ksps, Micropower Serial ADCs 12-Bit, 50ksps 8-Channel Serial ADC 12-Bit, 46.5ksps 8-Channel Serial ADC 12-/14-Bit, 2.8Msps Serial ADCs 12-/14-Bit, 3Msps Simultaneous Sampling ADCs 14-Bit, 400ksps Serial ADC 16-Bit, 200ksps Serial ADC 12-Bit, 5V, 250ksps Serial ADCs 16-Bit, 5V, 250ksps Serial ADCs COMMENTS 0.48mW, 1 or 2 Channel Input, SO-8 1.25mW, 1 or 2 Channel Input, SO-8 5V or 5V Input Range, 30mW, Full-duplex 5V or 5V Input Range, 30mW, Half-duplex 3V, 15mW, MSOP Package 3V, 14mW, 2-Channel Differential Inputs, MSOP Package 5V or 5V, 20mW, Internal Reference, SSOP-16 5V, Configurable Bipolar or Unipolar Inputs to 10V 1.22mW, 1-/2-Channel Inputs, MSOP and SO-8 4.25mW, 1-/2-Channel Inputs, MSOP and SO-8 1.22mW, 1-/2-Channel Inputs, MSOP and SO-8 4.25mW, 1-/2-Channel Inputs, MSOP and SO-8
LTC1860L/LTC1861L 12-Bit, 3V, 150ksps Serial ADCs LTC1864L/LTC1864L 16-Bit, 3V, 150KSPS Serial ADCs
1400fa
20 Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
LT 0606 REV A * PRINTED IN USA
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2006

▲Up To Search▲

Price & Availability of LTC14001

	To Download LTC14001 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .